# Can't make sense from VHDL butterworth filter implementation

I am trying to understand the VHDL implementation of the 3rd order Butterworth filter published on opencores. Supposedly the filter implementation gets away with only division and multiplications by 2 which is cheap when implemented in hardware (only shifting the bits left/right).

I've translated the VHDL to MATLAB to simulate a step response.

x = int16([zeros(1,500) 512*ones(1,1000)]); % step-input

a = zeros(1,3); % accumulator registers
w = zeros(1,5); % analog filter state variables

s = 4; % scaling parameter to adjust cutoff frequency

for t=1:length(x)
in = x(t);

a1 = a(1) + w(1) - w(3);
a2 = a(2) + w(2) - w(4);
a3 = a(3) + w(3) - w(5);

w1 = in - w(2);
w2 = a(1)/power(2,s);
w3 = a(2)/power(2,s+1);
w4 = a(3)/power(2,s);
w5 = w(4);

% update registers for next cycle
a = [a1 a2 a3];
w = [w1 w2 w3 w4 w5];
y(t) = 2*w(5);
end


The step response looks quite promising; dotted line is the step input, solid red, orange and blue are the filter response for s=3, 4 and 5 respectively. However, the implementation really does not make much sense to me. Can anyone enlighten me? What are the coefficients of the filter? Which form does the implementation follow?

The filter structure is a digital leapfrog and the structure looks like this picture (note: the picture is a different order than the code): 