I am implementing a GNG using Verilog. The implementation is based on the IEEE paper "Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method". In this, i could not understand what exactly does the ROM_trans block needs to store. I understand it is a lookup table, but I do not know what to store inside it. Also how will I determine the coefficients that need to be stored in the ROM_coef block.

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2 Answers 2


My friend, you dont need to break your head against a paper...

Just with any example of this list, the Blum Blum Shub Method:

$$x'_{{n+1}}=x_{n}^{'2}{\bmod M}$$

with $M=pq$, $p$, $q$ primes, with $x=\frac{1}{M}x' \approx U(0,1)$ gives you a fairly acceptable uniform $U(0,1)$ random number generator. You can use $p$=13331 and $q$=131 or whatever other.

And for converting the $U(0,1)$ Uniform Random Number into a $N(0,1)$ Gaussian Number Generator, as in here, just can use the Central Limit Theorem to generate N numbers each step, and make the sum (Bates Distribution). You can use $N$=15:

$$y'_{n}=\frac{1}{N}\sum_{i=1}^N x_{n}^i$$

with $y=\sqrt{12N}(y'-\frac{1}{2}) \approx N(0,1)$

For randomizing, just use a clock or cpu time seed as $x_0'$.


The paper does not give much details. As a partial answer, I would suggest you to parse the Ph. D. thesis of the first author: Implementación de Funciones Elementales en Dispositivos FPGA, Julio 2011.

Even if the thesis is in castellano, you can find several more occurrences of the terms ROM_coef and ROM_trans, for instance in the algorithm description Algoritmo Segmentación no-uniforme ICDF on page 130.

And some online translators can help you convert:

Finalmente comprobamos si hemos llegado al valor de sigma vs pedido y si es así finalizamos el bucle while y llamamos a una función esc_rom_vhdl que genera los ficheros vhdl que modelan el comportamiento de la memoria ROM_coef y ROM_trans utilizados en nuestra implementación.

into something readable in English:

Finally we check if we have reached the value of sigma vs. order and if so we finish the loop While and call a function esc_rom_vhdl that generates the vhdl files that model the ROM_coef and ROM_trans memory behavior used in our implementation.


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