# How to perform downconversion using a DSP

I read that to perform downconversion, first, I need to generate a sine wave with the same phase and frequency as the transmitter's and then multiply the signal received by the generated sine wave. I don't know how to do that, I think I have a way to generate the synchronized sine wave, but I don't know how to perform the multiplication.

I read that I can use a mixer or a nonlinear circuit to perform the multiplication, but I have a DSP and it doesn't have a frequency mixer available. Can I do it digitally ? The carrier has 125kHz and the modulating signal has 20kHz. I can use a sampling rate up to 1MHz and the DSP can reach up to 70 MIPS.

I'm sorry if my explanation is incomplete, I am really studyng the problem, so if you need more information you can ask and I will try to make the question more complete.

With my best regards,

Daniel.

• what analog filters do you have before sampling (anti-aliasing)? – Marcus Müller Nov 21 '16 at 14:34

Yes, you can do the operation digitally; this is a very common operation in modern software-defined radio systems. The implementation is straightforward: you just implement the same steps that you would see in a hardware implementation. First, multiply by a sinusoid at the carrier frequency, then apply a lowpass filter to remove any images.

• You mean I just need to multiply sample by sample ? I ask this because I generate the synchronized sine wave outside the DSP, so, I will sample both, the generated synchronized sine wave and the signal, at the same time, and perform the multiplication ? – Daniel Nov 21 '16 at 17:36
• Why do you generate the sine wave outside? That sounds like a bad thing to do. – Marcus Müller Nov 21 '16 at 19:34
• Because I'm thinking in how to do this synchronization. I don't know how to do it all in software, so I was thinking to use an external comparator to perform frequency synchronization ( It sinalizes each cicle begining ). But, unfortunatelly, I don't know yet how to perform phase synchronyzation. – Daniel Nov 22 '16 at 11:48

# Implementation of the Oscillator & Multiplication

In DSPs, ressources are sparse. Therefore, "just" calculating $\sin(2\pi f n),\,n=0,1,\ldots$ isn't all that easy. There's different ways of synthesizing an oscillation – be it a large look-up table for $\sin$ values (not very flexible with respect to different $f$) , or a look-up table through which you jump at different strides (and wrap around), or something to iteratively approximate the sine through exploitation of its taylor series.

I'd like to warn you about the CORDIC. It's still taught in many places as the appropriate tool to approximate trigonometric functions on microcontrollers, but nowadays, you simply wouldn't use a microcontroller without an arithmetic unit that can do arbitrary multiplications, and you espeically won't find a DSP that doesn't have a multiplication instruction. The CORDIC's place is in FPGA/ASIC design, not on DSP cores! For signal processors with a reasonably fast multiplication (i.e. all of the last ca. twenty years), a simple taylor-based approximation, often combined with a LUT to increase accuracy slightly, is usually much better.

# Application of undersampling

As you noted, your signal of interest is but $b=20\,\text{kHz}$ wide – sampling it at 1 MS/s does seem like a waste!

So, your signal is between $125 - \frac{20}2=115\,\text{kHz}$ and $125 + \frac{20}2=135\,\text{kHz}$.

Let's aim for a situation where you slightly oversample your signal.

Remember, you're sampling a real-valued signal with rate $f_s$, so the bandwidth observable is $\frac{f_s}2$ wide, and it will be symmetrical to $f=0$, and it will repeat with $f_s$ in frequency domain!

To sample a $b= 20\,\text{kHz}$ wide signal, a sampling rate of $f_{s,min}=40 \,\text{kHz}$ would be sufficient. Instead, let's simply choose a sampling rate of $100\,\text{kHz}$ and see what happens:

1. The signal around $f_0=125\,\text{kHz}$ ($\pm 10\,\text{kHz}$) will be shifted by $f_s$ to $(15\,\text{kHz} ; 35 \,\text{kHz})$.
2. Now, we have a signal on an IF (intermediate frequency of) $25\,\text{kHz}$ – congratulations, that is basically what a superheterodyne receiver would be, if it was analog!
3. Instead of sampling with twice the highest frequency, $f_{s,naive}\ge 2\left(f_0 + \frac b2\right)=2\cdot 135\,\text{kHz}=270\,\text{kHz}$, we were able to sample at a significantly lower rate, saving our CPU cycles to actually do useful stuff.

This of course requires that, by analog means, you make sure there's no analog signal between $15\,\text{kHz}$ and $35\,\text{kHz}$ – otherwise, that will overlay with the alias of your signal. Of course, you also have to make sure there's nothing in all $(15\,\text{kHz} + n\cdot f_s; 35\,\text{kHz} + n\cdot f_s)$ – but you'd need a normal anti-alias low-pass filter, anyway, so that doesn't mean additional effort.

Also notice that it's absolutely sufficient for your high-pass analog filter, which must cancel out everything below $35\,\text{kHz}$, to have a transition bandwidth of $(115-35)\,\text{kHz}=80\,\text{kHz}$ – that is relatively easy to do, e.g. with a two-opamp active filter.

# Elegant choice of digital LO frequency

The example above is nice – but it gives us the signal in $\pm 10\,\text{kHz}$ around $25\,\text{kHz}$. What if we, instead, want it as complex baseband around $0\,\text{Hz}$?

Now, the elegant choice of sampling rate pays off - shifting by $25 \,\text{kHz}$ and conversion to a complex signal can be very simple: we just need to generate and multiply witjh $e^{j2\pi \frac{f_\text{shift}n}{f_s}}=e^{j2\pi \frac{-25\,\text{kHz}}{100\,\text{kHz}}n}=e^{-j\frac\pi2n}$, and that only takes the values $1,-j,-1,j, 1,-j,\ldots$ – which is but a very simple sign change and assignment to either real, or imaginary part!

• Thank you Marcus Müller. You made a very good explanation, I'm reading it carefully. But, for now, I'm having trouble in how to implement the carrier synchronization. I can perform frequency synchronization, but, I can't perform phase syncronization yet. I'm using a dsPIC33EP and a external comparator to signalize each cicle begining. So, the comparator would signal the begining of the cicle and I would start to generate in dsp the software to perform the sine wave. But this method guarantees the frequency sinchronization, but does not guarantee phase sinchronization. Would you have any tip ? – Daniel Nov 22 '16 at 17:09
• I tried to perform downconversion by sampling, but it doesn't work as you can see in a question that I posted before and you can read in the link below: dsp.stackexchange.com/questions/35395/… I made a more detailed information about the situation here: dsp.stackexchange.com/questions/35408/… – Daniel Nov 22 '16 at 17:26
• @Daniel Phase sync is essentially timing sync, and how to do that depends on the type of signal you're receiving. – Marcus Müller Nov 22 '16 at 17:27
• By "the type of signal" you mean the kind of modulation, like AM or FM ? Because It is load modulation, a kind of AM. I described it a bit here: dsp.stackexchange.com/questions/35408/… – Daniel Nov 22 '16 at 17:41
• and yet no one upvoted this valuable answer.. sigh – Denis Dec 4 '18 at 3:44