# Clock Jitter and Phase Noise

I would like to know the impact of the time jitter of the clock driving an ADC on the appearing phase noise while sampling a sine wave. Of course, with strong the clock jitter, the sampled sine wave seems to exhibit more and more phase noise. But how much ? Regards, Mike

For a sine wave with a period $t_p$ the clock jitter or clock edge time error $t_j$ gives a phase error of $2 \pi t_j/t_p$ radians, where $2\pi$ represents a full period of a sine wave in terms of phase. The period $t_p$ of the sinusoid is an inverse of its frequency $f$, so the phase error can also be written as $2 \pi t_j f$. No matter if error is the peak error or the root mean square error, or whatever, as long as it is the same kind for both clock edge time error (jitter) and phase.

There are two sources of sampling jitter in ADCs namely clock jitter and sampler jitter (S/H circuit). Clock jitter or clock phase noise is due to clock imperfections. So if you have an idea sampler, your clock uncertainty will cause jitter in sampling process. On the other hand, with an ideal a clean clock with no jitter, but an non-ideal sampler, we will still observe jitter. This is due to transistor intrinsic-noise, which would cause deviations from exact sampling time, and is called sampler circuit jitter. $$\sigma_{system}^2=\sigma_{circuit}^2+\sigma_{clock}^2$$ So sampling jitter is assumed as random deviations of actual sampling instances from desired sampling instances. As shown in following figure these random deviations transform into a random noise in the sampled signal. This noise is proportional to the frequency of input signal and Standard Deviation (s.d) of jitter noise. Authors of [1] provided a model to quantify and estimate the jitter noise.

The model assumes the input signal is a single tone sinusoid sampled with Nyquist-rate. The authors showed sampling jitter has a Gaussian distribution with a mean of zero and a known standard deviation $$\sigma_{jn}$$ (based on circuit). Based on their work, the induced jitter noise is directly connected to the s.d of sampling jitter , and slop of the signal at the sampling point $$\left.\frac{dV}{dt}\right|_{rms}$$, where $$V=\cos(2\pi ft)$$:

$$e_j=\left.\frac{dV}{dt}\right|_{rms}\times \sigma_{jn}=\sqrt{\frac{1}{T} \int_0^T\left(\frac{dV(t)}{dt}\right)^2 dt}\times \sigma_{jn}=\sqrt{2} \pi fA\sigma_{jn}$$

where $$A$$ is the amplitude of the input sinusoid. Taking into account the jitter noise and the input noise, the SNR of the sampled signal, can be approximated by:

$$SNR_{sampled}=10\log_{10} \left[\left(\frac{A}{\sqrt{2}}\right)^2\bigg/\left\{(\sqrt{2} \pi fA\sigma_{jn} )^2+e_i^2\right\} \right]$$

if we consider the input noise (noise in signal before sampling) too small, $$(e_i \ll \sqrt{2} \pi fA\sigma_{jn} )$$, the above SNR formula would simplify to:

$$SNR_{sampled}=-10\log_{10}⁡(2 \pi f \sigma_{jn} )^2$$

which means how much SNR you loose in terms of jitter magnitude and the signal frequency.

Have a look for details in this paper:

M. Shinagawa, Y. Akazawa and T. Wakimoto, "Jitter analysis of high-speed sampling systems," in IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 220-224, Feb 1990.doi: 10.1109/4.50307

Phase noise is just a multiplicative noise affecting the signal. Let the un-distorted signal be $s(t) = e^{2\pi f_0 t}$. In the presence of phase noise: $$\tilde{s}(t) = s(t)e^{j\epsilon(t)}$$ where $\epsilon(t)$ is a stocahstic random process. Usually, $\epsilon(t) <<1$ then $$\tilde{s}(t) \simeq s(t) + j\epsilon(t)s(t)$$ which only affects the quadrature-component with respect to the received constellation. In other words, you receive the original signal $s(t)$ and an inteferer $j\epsilon(t)s(t)$.