# Architecture for high sample-rate FIR/IIR filter on FPGA or ASIC?

Assume we have a hardware (FPGA or ASIC) which can operate at a fixed processing frequency of $100\textrm{ MHz}$. Assume we have an input data stream of $1\textrm{GSPS}$ (which has been sampled using any SERDES interface, but here the sampling technique does not matter). We would like to implement a filter which can NOT be implemented by a poly-phase decimation filter; for example assume we want to implement a band-pass filter which passes the frequency range $200-300\textrm{ MHz}$ in our example.

• What architectures can be used for this purpose?
• Can anyone provide a reference for designing such filters?
• Your example could very well be implemented as polyphase decimator! – Marcus Müller Sep 3 '16 at 10:08

However, your example is exactly the standard example of a filter that can be implemented as a polyphase decimator: you get in 1000 MS/s, you filter to 100 MHz of that, and decimate by ten (note: assuming complex sampling here). You can do that, because your bandpass restricts the bandwidth that passes through to $\frac1{10}$ of the input bandwidth.