Assume we have a hardware (FPGA or ASIC) which can operate at a fixed processing frequency of $100\textrm{ MHz}$. Assume we have an input data stream of $1\textrm{GSPS}$ (which has been sampled using any SERDES interface, but here the sampling technique does not matter). We would like to implement a filter which can NOT be implemented by a poly-phase decimation filter; for example assume we want to implement a band-pass filter which passes the frequency range $200-300\textrm{ MHz}$ in our example.

  • What architectures can be used for this purpose?
  • Can anyone provide a reference for designing such filters?
  • $\begingroup$ Your example could very well be implemented as polyphase decimator! $\endgroup$ Sep 3, 2016 at 10:08

1 Answer 1


Short answer: If your sampling rate is higher than your throughput, you must use some kind of polyphase decomposition of your filters to work. So if you can't do that, you can't use a 100 MHz-clockable design to filter something with a sample rate of 1000 MS/s. It's as simple as that.

However, your example is exactly the standard example of a filter that can be implemented as a polyphase decimator: you get in 1000 MS/s, you filter to 100 MHz of that, and decimate by ten (note: assuming complex sampling here). You can do that, because your bandpass restricts the bandwidth that passes through to $\frac1{10}$ of the input bandwidth.

Anyway, even so, this will very probably not work out – there's simply zero margin for "real world" effects in your 100MHz clock to produce 100 MS/s, so you should really look into a design that can work faster.

Also, it's usually not that you buy an FPGA and can say "this works at 100MHz, no matter what I do on it", but you know its maximum clocking (which typically is much higher than 100MHz for devices that can take in 1GS/s via SERDES these days), and the maximum clock rate achievable depends on the DSP you do – so you can typically just ask your FPGA design tool to generate a FIR that is optimized for high rate (rather than e.g. for low power or small ressource consumption), and you'll get a different possible rate depending on what FIR architecture you chose.

  • 1
    $\begingroup$ Not wanting to revive an old thread. But in an FPGA, you could process a 1 Gigasamples/s data stream with a 100 MHz clock. You'd need to add parallel processing though. $\endgroup$
    – Ben
    May 25, 2021 at 11:29

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