I have this ADC and I have this 169p micro-controller. The system oscillator clock frequency (FOSC) is 8 MHz.

According to the ADC documentation the conversion process takes 16 cycles. So if I have FOSC of 8MHz would I get a sampling rate of 8000000/16 = 500,000 samples per second? The ADC has 4 channels so can I divide the sample rate by 4? 500000/4 = 125,000 samples each 16 bits (2 leading zeros, 2 for channel, 12 for conversion).


closed as off-topic by A_A, Gilles, MBaz, Marcus Müller, Peter K. Aug 31 '16 at 15:11

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  • $\begingroup$ this calculation relies on assumptions about a particular architecture of a specific chip. Instead you should better ask it to chip vendors. If you don't get a response, try doing some experimentation. The documentation should already be answering your question, but sometimes they can be unclear. $\endgroup$ – Fat32 Aug 30 '16 at 20:31

This question isn't particularly on-topic, but the answer is pretty simple. Look at the second paragraph of the General Description on the first page of the ADC datasheet:

The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is initiated at this point. There are no pipeline delays associated with the part.

CS in this case refers to the chip select pin on the ADC's SPI-compatible 4-wire serial bus. That signal is asserted each time the host processor initiates a transaction to the converter. The mechanics of an SPI read go like this:

  • The SPI master (i.e. the host processor) asserts the CS signal.
  • If the SPI master has any data to write to the device, it presents it in serial fashion on the MOSI (master out, slave in) signal. From the ADC's perspective, this would be the DIN pin.
  • The SPI master begins to apply a clock signal to the ADC on the SCLK pin. This is used to simultaneously shift data in and out of the ADC serially.
  • For this ADC device, the transaction continues for 16 bits. After that, the master has received 16 serial bits from the ADC, which contain the conversion result.
  • The master deasserts the CS pin to end the transaction.

In the above timeline, the speed of the conversion is therefore limited by two factors:

  1. The SPI clock rate (as it determines how long it takes to extract 16 bits).
  2. The maximum conversion rate that the ADC supports.

#2 in the above list is very clearly stated to be 1 MHz. #1 is dictated by the capabilities of your host processor, and can be found in the datasheet. Specifically, look at the bottom of page 166:

Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 18-5 ). This means that the minimum SCK period will be two CPU clock periods.

It is stated elsewhere in the datasheet that a "CPU clock period" as referenced here is equivalent to $\frac{1}{f_{OSC}}$. Therefore, if your processor has a CPU clock frequency of 8 MHz, its maximum SPI clock rate is:

$$ f_{max,SPI} = \frac{f_{OSC}}{2} = 4\text{ MHz} $$

Remember though that this is a serial bus with 16 bits per conversion transaction. Therefore, the maximum ADC sample rate is:

$$ f_{max,ADC} = \frac{f_{max,SPI}}{16} = 0.25\text{ MHz} $$

Thus, the processor is the limiting factor here; it can only support a maximum of a 250 kHz sample rate. Furthermore, this is the maximum throughput that is available to the entire ADC device, so if you're using more than one channel on the ADC, this 250 kHz would have to be split between the channels you're using.

  • $\begingroup$ Thank you so much for the knowledge exactly what I needed $\endgroup$ – wwjdm Aug 31 '16 at 18:11

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