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The problem I'm having concerns an add operation in verilog which is part of a transposed FIR filter.

add(a,delay_line[i],delay_line[i+1]);
  • a is an input from multiplying a cofficient with the current input sample.
  • delay_line[i] is an input from the delay line at index i
  • delay_line[i+1] is an output to the delay line at index i+1

The problem I have is that the add operation takes $3$ clock cycles. My new a input arrives every $1$ clock cycle, so as you can see ideally I would need the add operation to take one clock cycle, then the inputs to the add are at the same rate, and can update the delay_line correctly. I'm sure doing an add in one clock cycle is fine in practice, but in the case where it is not, then how can this be resolved ?.

My first approach was to draw out the filter structure and add more delay taps on the ouputs of adds. The normal FIR transpose filter has single $z^{-1}$ delays after each addition, so I placed some $z^{-3}$ delays to compensate for the add delays. doing that wrecks the frequency response so its not that simple :)

I initially thought this was a Verilog / FPGA problem, but I think this is more of a DSP algorithm problem now so I posted it to this forum. If someone can point me to some literature on this that would be appreciated.

Here's my attempt to model this in MATLAB (sorry if you don't have this tool)

%this is an fir transpose filter
fre = ( [0 1500 1700 4000]/4000) ;
msk = [1 1 0 0]; %mask
b = firpm(3,fre,msk); %simple 4 coefficient low pass

%convert filter to transposed form 
Hd = dfilt.dffirt(b);
b = cell2mat(Hd.coefficients);

bd2 = [b(1) 0 0 b(2) 0 0 b(3) 0 0 b(4)]; %never this simple!

fvtool(b,1,bd2,1);%compare frequency response 
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Ah, its easier than I thought, just mirror the introduced delays. So this means introduce two additional $z^{-2}$ in the last two stages of the transpose FIR filter structure. After some basic math to get $H(z)$ the coefficients are as below in bd2, which gives the same magnitude frequency response as the original.

bd2 = [0 0 0 0 b(1) b(2) b(3) b(4)];
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