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I need to generate sine and cosine signals using DDFS (Direct Digital Frequency Synthesizer.) I'm unable to get the idea of the phase increment applied as input which changes the frequency of the quadrature signals.

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A Direct Digital Frequency Synthesizer (DDFS) or simply Direct Digital Synthesizer (DDS) usually refers to the combination of a Numerically Controlled Oscillator (NCO) combined with Digital to Analog (D/A) converters for complex quadrature output or a single D/A converter for a real output.

An NCO is actually a fairly simple structure, consisting of a Frequency Control Word (FCW) input to a "phase accumulator" which is nothing more than a simple counter, usually of high precision, and counts in increments of the FCW. Note that an accumulator is a digital integrator (for example in continuous time, the integration of a constant is a ramp; in discrete time, an input of all ones into an accumulator [1 1 1 1 1 ...] would also be a ramp [1 2 3 4 5 ...]. For this reason, if we say the input that is just a digital value represents frequency, and knowing that the integration of frequency is phase ($freq = \frac{d\phi}{dt}$), then we can therefore see that the accumulator output represents phase (so we call it the phase accumulator). Since the output of the counter is phase versus time, we then need a function to convert that to a sine wave (or sine and cosine wave for quadrature output). This is often done with a lookup table (LUT), that will function as a calculation of the sine and cosine values for the specific phase values at a given time in the phase accumulator. The output of the LUT will therefore be the (digital) sine and cosine functions versus time, with a rate that is set by the input FCW (A higher FCW will result in a higher count rate at the phase accumulator output, meaning more cycles in time of our sine and cosine waveforms at the LUT output. The LUT will contain exactly one cycle of the sine and cosine waves (effectively, memory compression algorithms are actually used so that less data needs to be stored), so as the phase accumulator rolls over properly ($Cnt_{max}+n = n$), the output sine and cosine waves continue where expected without interruption.

Here are some slides I have that describe the NCO. Also included in the figure is the Phase Control Word (PCW), which is an offset control for the Phase Accumulator Output, providing direct phase modulation control if desired:


NCO Implementation view:

NCO Block Diagram


NCO Mathematical view (continuous time equivalent):

NCO Mathematical View



In implementation, the phase accumulator is typically quite large in precision (24 to 48 bits), driven by the frequency step size desired. The frequency control word is of a similar size (usually 1 bit less to synthesize all frequencies from DC to $F_{clk}/2$). Since the LUT contains one cycle of the output frequency, counting through every value in the accumulator means counting through every address in the LUT, and this would result in the lowest possible output frequency above DC. Counting by 2 would result in a frequency twice as fast, and so on. From this we easily see the relationship:

$F_{step} = \frac{F_{clk}}{2^{acc}}$

and

$F_{out} = FCW * F_{step}$

Where

$F_{step}$ is the step size in Hz

$F_{clk}$ is the clock rate that the accumulator updates in Hz

$acc$ is the accumulator size in bits

$F_{out}$ is the output frequency in Hz

$FCW$ is the Frequency Control Word in digital counts. [0 to $(2^{acc-1})-1$]

Phase Truncation, SFDR and SNR

If we passed all the phase accumulator bits to a LUT, the digital output for each frequency control word would be perfect, with the only error source being the precision of the sine wave stored in memory (defined by the LUT output bit width). However the memory requirements for such an implementation would be excessive, and given the resulting noise, unnecessary. Therefore we truncate the LSBs of the phase, leading to truncation error in the frequency output. This results in spurs throughout the frequency spectrum, based on the repetition rates of the truncation patterns that are created. The relationship between the highest spur and the phase truncation comes out very nicely as 6.02 dB/bit where bit is the number of MSB bits that are passed on after truncation. For example, in the figure shown, 14 bits are passed on after truncation, so the Spurious Free Dynamic Range (due to phase truncation errors) is 6.02*14 = 84.28 dB. This means, that although there are lots of spurs all across the digital frequency spectrum (from DC to Fs) but the strongest of all the spurs, in this case, is -84 dB below the output signal level. (At least the strongest of the spurs due to the phase truncation that was added).

I had also evaluated the SNR (signal to noise ratio, where in this case the noise is due to the combined power of all spurs from phase truncation) and this came out to be

SNR due to phase truncation:

$SNR = 6.02dB/bit - 5.172 dB$

here, bit is the number of bits into the LUT

So this means for our example with 14 bits after truncation, the combined power of ALL spurs created from phase truncation would be (6.02*14 - 5.17) = 79.11 dB below the output signal. The strongest of the spurs was 84.28 dB down as calculated previously, so this means all the other truncation spurs increase the total spurious noise power by 5.17 dB. Note that are values for FCW that will result in a spurious free output (spuriuos free of spurs due to phase truncation), all FCW values that keep the truncated bits always at 0 - an example of this specific to the figure below where there are 18 truncated bits, is an FCW of 1+[eighteen zeros] = 262144 decimal) . However for all other values, and sufficiently long data runs, these formulas will apply.

This relationship was derived by making use of the fact that the phase truncation error is a ramp or cyclically sampled ramp, which has a uniform distribution. This is a useful relationship that can be combined with the well documented quantization noise of a full scale sine wave (referring to the digital output after the look-up table), as:

SNR due to output quantization:

$SNR = 6.02 dB/bit + 1.76 dB$

here, bit is the number of bits out of the LUT (or effective number of bit, ENOB of the ADC if considering the ADC output).

Quantization noise and phase truncation noise can reasonably be considered independent and uncorrelated, meaning the total noise for a composite SNR would sum in power. Therefore the above two SNR relationships can be very useful in establishing the overall noise performance, leading to the precision requirements on the NCO both at the input and output side of the LUT, while the accumulator size itself is driven from the frequency resolution desired.

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  • $\begingroup$ Still confused about FCW. How does it control the rate? What should be its values? What is it that will be accumulated to give phase?bits? $\endgroup$
    – Sumbul
    Commented Jun 16, 2016 at 10:07
  • $\begingroup$ To highlight what I wrote on FCW: FCW is a digital word that sets the count rate in the accumulator: if FCW was decimal 1, the accumulator would count by 1 which is the slowest rate (accumulator = 0,1,2,3,...). If FCW was decimal 2, the accumulator would count by 2 which is twice as fast (0,2,4,6,8....) If FCW was decimal 3 the accumulator would count by 3 (0,3,6,9...) which is 3 times as fast. The output of the accumulator represents phase, so FCW is controlling the rate of phase. The rate of phase is frequency. I gave the formula for FCW based on the frequency step size you want. $\endgroup$ Commented Jun 16, 2016 at 10:47
  • $\begingroup$ To calculate FCW: $FCW = \frac{F_{out}}{F_{step}$ where $F_{out}$ is the output frequency desired, and $F_{step} = \frac{F_{clk}}{2^{acc}}$ where $F_{clk}$ is the master clock rate (how fast the accumulator updates) and acc is your accumulator size in bits. Example for a 100MHz master clock and a 32 bit accumulator, the step size is $F_{step}= 100e^6/2^{32} = 0.023$ Hz, and to set a frequency closest to 9.5MHz use an $FCW = (9.5e^6)(2^{32})/100e^6 = 408 (decimal) which is 110011000. Hopefully this clears it up for you! $\endgroup$ Commented Jun 16, 2016 at 10:58
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    $\begingroup$ The contents of the LUT will be the values for a cosine(phase) where phase goes from [0: N-1]*2pi, and the truncated accumulator will be the address to the LUT going from 0 to N-1. This way the LUT contains one cycle of the cosine wave. (Actual implementations only need to store a 1/4 cycle as the other values are redundant, and then have special logic to decide when to count up, down, forward and backward- but you don't need to do this now but wanted you to be aware. Did you read/understand everything I wrote above? I fear you might be missing some important.design concepts. $\endgroup$ Commented Jun 16, 2016 at 22:39
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    $\begingroup$ Once you have the FCW in decimal form, you simply count in increments of that FCW value (that's what it means to "integrate"). $\phi[n]=\phi[n-1]+FCW$. Is that what you are doing? The Phase Truncation, SFDR and SNR discussion is important if you need to really understand the noise performance of your system. If you know your SNR requirements then this would be more of interest. What is important for you to understand is that only the MSB's of the phase accumulator need to go to the LUT--- the less MSB's you use, the more phase truncation you will get, resulting in more noise. $\endgroup$ Commented Jun 17, 2016 at 10:09

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