# Linearizing digital-analog converters

I'm looking at ways to improve the effective resolution of DACs. It seems that element mismatch (i.e. integral non-linearity) is the main contributor to distortion in modern DACs. Apart from calibrating current sources and trimming resistors -- what signal processing solutions exist to reduce distortion in DACs (that improves the (effective) linearity)?

To give a few criteria:

• target rate should be around 100kS/s
• Need 20 bit ENOB, best I can find 16 bit ENOB
• Both requirement for 20 bit accuracy in DC, and low distortion in dynamic usage
• The interesting question here is the reason you're looking at DAC linearity: Is it really just the need to have a "stationary exact" value, or is it that you need to suppress the intermodulations that happen due to nonlinearity? Could you give us an idea about the order of magnitude of Samples per second, bits, and acceptable nonlinearity, too? May 26 '16 at 21:50
• So the reason for looking at the linearity, is that the noise floor of new DACs seem to be very low, but the non-linearity generates enough harmonic distortion to actually be a significant disturbance source in the systems we are working on (high precision). We need both exact DC, and we want to remove as much distortion and noise as possible when using a time-varying signal. Ideally we want to get to an ENOB of about 20-bit, and with a sample rate of up to 100 kS/s or so... We have tested a slew of commercial DACs, best one so far yields an ENOB of 16-bit or so. Thanks! May 27 '16 at 0:02
• So, I'll have to sleep over this. The good news: at 100kS/s, assuming you control this from something about as capable as any PC, or embedded Linux device, predistortion, even with a complex polynomial, is an option. The same goes for dithering; that rate is computationally not that demanding. You can just 100-fold oversample your signal in your controller (to something like 10MS/s), and "dither down" from that high rate signal, by using slightly varying decimation "offsets". May 27 '16 at 0:13
• What about analog.com/en/products/digital-to-analog-converters/… ? 20bit resolution, nonlinearity is relatively low May 27 '16 at 0:18
• Sounds interesting, I would be very interested in a more in-depth explanation of the method :) Computational power is not really an issue, by the way. The fastest we can reliably stream to a DAC so far is about 5-10 MS/s, but the fast parallel interface DACs appear to be very non-linear... May 27 '16 at 0:21

well i'm assuming you mean "conventional" DACs and not $\Sigma \Delta$ DACs.

in a conventional DAC (like an R-2R ladder or something), there are the micro errors that occur between neighboring DAC codes. e.g. non-monotonicity. i think the DSP solution to that is adding a teeny amount dither noise to the value that is output to the DAC.

there is a more macro nonlinearity that one can see in the DAC code to voltage curve. the curve should be a straight line, but isn't exactly. to linearize that, you need to compute the inverse curve and put that into a lookup table and process the output to your DAC through the lookup table before outputting it.

all this requires getting to know the specific non-linear faults of your conventional DAC first. to do that requires an ADC (that the DAC output is connected to) that you trust or many repeated measurements with analog dither and various DC offsets added to the ADC input to smooth out the crap in the ADC.

• Thanks for that! I didn't have any specific architecture in mind, but yes, conventional DACs are probably more amenable to improvement. How do you figure a lookup-table would work when the output is quantized? The actual errouneous output levels would still be the same... About the measurement: It sound like it might be a method described in detail somewhere, any references? Thanks again May 25 '16 at 4:30
• the lookup table is for the gross nonlinearity. the macro-nonlinearity. not the micro nonlinearity, which i think can really only be dithered to sorta remove that effect. May 25 '16 at 4:33
• and i don't think the $\Sigma \Delta$ DACs would even have this kind of non-linearity. they have problems if the upslope is not the same as the downslope on the binary output. but the math done inside that sorta does PWM is linear. the duty cycle of the DAC output should be linear with the DAC code. May 25 '16 at 4:35
• the fancy new multi-bit $\Sigma \Delta$ DACs do... you are right about the quantization error and dither -- I'm not sure the gross non-linearity would be affected much by a look-up table, but I'll give it a try, thanks! May 25 '16 at 4:40
• using a lookup table to undo the gross non-linearity of a particular DAC requires knowing the specific gross non-linearity of that particular DAC. this is not a mass-production solution. it is simply inverting that static function of the gross non-linearity. May 25 '16 at 17:16

Another typical approach, that independently of my other answer works, is predistortion, for example with the look-up table mentioned by robert, or with a correction polynomial.

If you can really pinpoint your nonlinearities to a simple digital-in/analog out curve, you can just find the inverse of that curve, and put it in a correcting mapping, and apply that to your samples; if these errors depend on dynamic properties of your signal, it might be worth to try the same with an oversampled signal – maybe an oversampling factor of 8 might totally suffice, here.

• Yes, this seems to come up in a few different settings. If I understand you correctly, given the non-linear transfer $y = f(x)$ you suggest finding an approximate function $g(x)$ such that $y = f(g(x)) = x$. I.e. $f(x) = x^2$ and $g(x) = \sqrt{x}$, for $x \geq 0$. I think this can work to reduce any non-linearity in the analog filters etc., but since the quantization process is a many-to-one mapping, I'm not sure the look-up table directly will be very effective for the raw output of the DAC... But, it gave me a couple of ideas to work with. Thanks for that :) May 30 '16 at 6:17
• @Arnfinn really try reducing the "many" to one by using oversampling. May 30 '16 at 6:53
• I'll look into the oversampling shortly :) I think the closest you get to predistortion for a DAC is described here: ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=409378&tag=1 May 31 '16 at 0:37
• They sum the output of two DACs, scaling one to approx. 1 LSB, then using that to cancel the errors in each level... May 31 '16 at 0:37

So, the intuitive reaction to this situation is oversampling.

Basically, if you use twice the sampling rate, you can always average to samples to get one "output sample value" (thanks, Nyquist!). That would give you one bit of additional per every oversampling factor of two, or

$$\Delta b = \log_2\frac{f_\text{sample}}{f_\text{target}}$$

Let's introduce the oversampling factor $m=\frac{f_\text{sample}}{f_\text{target}}$ and look at the improve in resolution $\Delta r$:

\begin{align} \Delta b &= \log_2\frac{f_\text{sample}}{f_\text{target}}\\ &= \log_2 m\\ &\implies\\ \Delta r &= 2^{\Delta b}\\ &=2^{\log_2 m}\\ &= m \end{align}

Woohoo! We've got an increase in resolution that's linear to the oversampling factor!

Sadly, noise increases with bandwidth; Johnson-Nyquist Noise being

$$N_0 = k_B \, T\, B$$

with $k_B$ the Boltzmann constante ($\approx 1.38\cdot 10^{-23}\frac{\text{J}}{\text{K}}$), $T$ the temperature and $B$ the bandwidth. Hence,

\begin{align} \Delta N_0 &= \frac{k_B \, T\, f_\text{sample}}{k_B \, T\, f_\text{target}}\\ &= \frac{f_\text{sample}}{f_\text{target}} \\ &= m \text{ .} \end{align}

Remember that voltage goes with the square root of power, so

$$\Delta \sigma_0 = \sqrt{m}\text{ .}$$

So, due to the increase of bitdepth being countered by an increase of noise, the resolution will only get better by $\sqrt m$.

Which means that for a ENOB increase of e.g. 4 bit, you will need an oversampling factor of $2^{2\Delta\text{ENOB}}$, i.e. $m=2^8$.

$$f_\text{sample} = 2^8 \, f_\text{target} = 25.6\,\frac{\text{MS}}{\text{s}}$$

would hence be sufficient if you had a 16bit DAC running at that rate, fed with a properly interpolated signal.

As mentioned, with a modern PC platform, doing that interpolation shouldn't be that hard. I whipped up a flow graph that exploits nothing of the fact that my PC has more than one core, or that $2^8$ could easily be decomposed to a cascade of half-band interpolators with GNU Radio Companion:

lpf is a 617 tap monster of a low pass FIR used to suppress images, and this still runs at more than 80 MS/s.

Now, let's talk about hardware I actually know (Disclaimer: I'm affiliated with that company. I'll still be honest about device facts; in the end, things fall back on me if I don't.), because that's exactly the place where I see that principle in full action. So please don't take this as advertisement, but as illustration.

So let's consider the USRP X300 or X310:

It has

• a gigabit or 10Gigabit Ethernet port to take in samples,
• a DAC supplied with 200MS/s and
• FPGA logic in between that uses appropriate filters/interpolators to generate the 200MS/s stream fram whatever $\frac{200\,\frac{\text{MS}}{\text s}}m$ sampling rate (which would be your $f_\text{target}$, here) the user chose to send from his computer to the USRP.

Notice that this implements exactly the resolution-gaining oversampling!

The DAC is the AD9146, a device that achieves maybe 13 bits of ENOB at 200MS/s. Now, for software defined radio applications, this is typically plenty (SNR being limited by many, many other factors). So we need an interpolation of a total of $2^14=16348$, so a sampling rate of 16.something GS/s. Not possible. We can cheat a bit – the USRPs are meant to produce complex baseband, so they have a dual-DAC, which means you could gain another $\frac{1}{\sqrt{2}}$ bit by using a summer on the two outputs, but that's it.

Now, if you could adapt that architecture (look at the N210; it's a predecessor of the X3xx, but with a 100MS/s DAC), which happens to be GPL-licensed Verilog, to work with your own 16 bit ENOB, >= 25.6MS/s DAC, you'd probably be fine.