1
$\begingroup$

I'm new to SP Stack Exchange . I am doing a project on implementing a handwriting recognition machine using Neural Networks in Real Time .

The Image Processing Part involves convolving a 4*5 kernel over a 28*28 image. I want to know the pros and cons involved with using a DSP vs FPGA .

The FPGA I plan to use belongs to Xilinx's Spartan 6 family which has 90 DSP slices. Each DSP Slice has 18*18 bit MAC units which can operate in parallel at 200MHz.

My college has a DSP starter kit TMS320C6713 DSK from Spectrum DIGITAL. I'm not sure how MAC operations are performed in DSP .Do we have parallel MAC units? The datasheet isn't very clear on the MAC units .

Are there any advantages on using the DSP over the FPGA which I might have overlooked?

Any help is appreciated .

$\endgroup$
  • $\begingroup$ I did not like the response since it misses one advantage the DSP has over MAC implementation (conceptually may be implemented with the FPGA as well) - implement fast convolution utilizing 2d FFT/IFFT. In your case, implement it on a 32X32 image. Evaluate the number of multiplies you need to achieve the fast convolution vs the direct calculation. $\endgroup$ – Moti Jan 17 '16 at 1:40
0
$\begingroup$

At a high level, it's a relatively simple tradeoff: software development for DSP or general-purpose microprocessors is typically much less labor-intensive than FPGA development. At the same time, the amount of computational throughput offered by an FPGA typically far exceeds what a CPU can do, because you can tailor the logic specifically for your application.

Most any processor that is advertised for "DSP" will have multiply-accumulate (MAC) instructions available, and it is common for DSP processors to be able to execute multiple instructions per cycle. If you read the specifications for TI's C6713, you'll see that they advertise that it can complete up to 8 instructions per cycle (not necessarily all MACs, but a mix of several types of instructions). Note that it is pretty difficult to get close to that throughput, but it is possible if you invest enough effort learning how the architecture works and structuring your code accordingly.

One other major difference between an FPGA implementation and the particular DSP that you noted is that the C6713 supports native floating-point capability (instead of just fixed-point). For some applications, this can make algorithm implementation much simpler, as you don't have to worry about the issues that come along with fixed-point computations. While it is possible to implement floating-point computations in an FPGA, such an implementation would be much more demanding on the hardware, so depending on how complex your algorithm is, you might run into issues with resource utilization, achievable clock speed, and so on.

You should start by quantifying what kind of computational demands your algorithm is going to place on your hardware. Then, decide how much engineering time you can allocate to the project; from there, the choice will likely be clear.

$\endgroup$
  • $\begingroup$ @Jason your answer would be complete if it would discuss the fast coevolution using FFT $\endgroup$ – Moti Jan 17 '16 at 1:41
  • $\begingroup$ I don't see how that's relevant to this discussion. $\endgroup$ – Jason R Jan 17 '16 at 2:15

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.