For a lock-in amplifier I am downsampling the demodulated baseband signal prior to the final low pass filtering. This lock-in amplifier is implemented on an FPGA (myRIO of National Instruments).

Therefore I use CIC filters. I've reading a lot in Hogenauers paper and in "Understanding digial signal processing", by Richard Lyons. My downsampling rates are between 512 and 2048 (always powers of 2) as I want to decimate my input signal down to less than 100 Hz (e.g. 48kHz sampling will be decimated to 93Hz).

The gain of the CIC output is scaled to the CICs input by a simple bitshift afterwards.

Is there any disadvantage using even higher decimation rates?

  • $\begingroup$ Only if you have any bandwidth. If you are sampling a tone, any decimation is ok. You'll find in literature that many cic filters are followed by another filter to compensate the cic's roll off $\endgroup$
    – johnnymopo
    Jan 10 '16 at 16:58
  • $\begingroup$ They are often followed by filter to compensate the passband droop. As my signal is at 0Hz I dont care about the droop. Thank you for your answer. $\endgroup$
    – Slev1n
    Jan 10 '16 at 17:15
  • $\begingroup$ You say signal, to be clear, that obviously means baseband, but what about bandwidth? If you can arbitrarily lowpass filter, then you are ok. Sounds like you are $\endgroup$
    – johnnymopo
    Jan 10 '16 at 17:40
  • $\begingroup$ I've used very high decimation cic filters for static stepped frequency radar - the signal is always a baseband tone so any decimation was ok $\endgroup$
    – johnnymopo
    Jan 10 '16 at 17:42
  • $\begingroup$ The incoming signal is at a known frequency (~4kHz). The application is a lock in amplifier. Now the signal is demodulated to 0Hz and 2*f, whereby the 2*f part is being filtered later. So yes, the band of interest has more or less a width of 0Hz or at least in the low mHz scale. $\endgroup$
    – Slev1n
    Jan 10 '16 at 17:43

CIC filters don't have very steep roll-off, or a very flat passband. That's the downside of using this very special class of filters.

Other than that, you should be fine. However, as with every filter design, you will have to design, and verify, yourself to ensure the filter matches your requirements.

However, CICs are very often used as runtime-adjustable filters; and that works pretty well if you have e.g. high-quality Nyquist-M (especially halfband) FIRs. An example of this is the Ettus USRP signal processing DDC:

   // CIC decimator  24 bit I/O
   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(ddc_enb),.rate(cic_decim_rate),
               .strobe_fast(1),.strobe_slow(strobe_cic) );

   cic_decim #(.bw(WIDTH))
     decim_i (.clock(clk),.reset(rst),.enable(ddc_enb),

   cic_decim #(.bw(WIDTH))
     decim_q (.clock(clk),.reset(rst),.enable(ddc_enb),

   // First (small) halfband  24 bit I/O
   small_hb_dec #(.WIDTH(WIDTH)) small_hb_i

   small_hb_dec #(.WIDTH(WIDTH)) small_hb_q

   // Second (large) halfband  24 bit I/O
   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
   hb_dec #(.WIDTH(WIDTH)) hb_i

   hb_dec #(.WIDTH(WIDTH)) hb_q

The job of this chain is to decimate a 100MS/s signal down, adjustably, down to rates of 1/512.

Generally, if you just want to use powers of two, you can just use the same halfband filter multiple times; if you're doing it elegantly, you can probably even multiplex the same hardware for multiple iterations.

By the way, coming from a background where sample rates are in the MS/s, I wonder why you need such a low-rate decimation in hardware – every CPU can do that, nowadays, without breaking a sweat.

  • $\begingroup$ Thanks for your answer. As my frequency of interest is at 0Hz steepness is fine enough for the anti aliasing and the droop in the passband is no issue either. I need to get low, because my SNR is very bad ~-50dB this is varrying alot. And I have to low pass filter this signal very hard to improve my SNR, but filters with cut off frequencies at 0.01Hz or less with an input sampling rate of 48kHz or 280kHz, depending on the previous sampling rate, cant be implement efficiently (too many coefficients). $\endgroup$
    – Slev1n
    Jan 12 '16 at 17:30
  • $\begingroup$ @Slev1n nah, halfband filters aren't that hard to implement, and you could just concatenate multiple ones. Also, at these rates, having a few more taps shouldn't be a problem -- you can just multiplex a single DSP slice for a lot of taps; they run at hundreds of MHz. $\endgroup$ Jan 13 '16 at 10:27
  • $\begingroup$ Your bad SNR restriction definitely calls for concatenated "good" filters rather than CICs. $\endgroup$ Jan 13 '16 at 10:36
  • $\begingroup$ @MarcusMüller Hi Marcus, are you suggesting to use Halfband filters in this case? Or are you suggesting to combine CIC and halfband filters together? $\endgroup$ Mar 23 '16 at 8:21
  • $\begingroup$ @richieqianle That's kind of a broad question. Problem is that a filter that should filter to a cutoff frequency of 0.01 Hz of an input bandwidth of 280 kHz/2 would be a $\frac{1}{14\,000}$-band filter; which is terrible, because it would be really really long if the transition width would have to be in the same order of magnitude; a hundred-thousand-tap filter isn't feasible for a lot of reasons (latency, math stability, design approximations…). So you'd compose that filter from multiple other, decimating filters. Since halfband filters are extremely efficient to implement in hardware, $\endgroup$ Mar 23 '16 at 8:51

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