Consider a digital signal processing algorithm that operates over a block of $L$ [samples], with a real-time constraint $\tau$ [s] (i.e. its throughput must be $L/\tau$ [samples/s]).

The theoretical complexity of the algorithm is known, both in terms of arithmetic operations (additions, multiplications and comparisons) and memory accesses.

Is there any rule of thumb to get a (rough) estimate of the power consumption of this algorithm for typical hardware implementations (e.g FPGA, ASIC, General Purpose Processor, etc.)?

  • $\begingroup$ In a lot of cases, the complexity and throughput will steer you to a type of platform (e.g. an FPGA versus a general purpose processor or low power DSP). Will you use fixed point or floating point? How much memory does your processing require? Answering questions like these will often get you to the overall type of device. From there, you can estimate the number of operations needed per second, which steers you to a required clock frequency. Power consumption is then a function of clock rate; you can then arrive at an estimate. $\endgroup$ – Jason R Oct 30 '15 at 13:11
  • $\begingroup$ Thank you for your comment. I'm actually expecting an answer considering both fixed and floating point cases. I know this is a broad question. My ultimate objective is to get a complete framework to benchmark different implementations, and for that I need to get a full understanding of all the variables and processes that influence power consumption, and how they do it (at least for FPGAs and GPPs). I know it is linked to clock rate, but what is the nature of this relation? (e.g. linear? how does complexity affects it?) Answers linking to external references are of course welcome. $\endgroup$ – vaz Nov 2 '15 at 9:44

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