Consider a digital signal processing algorithm that operates over a block of $L$ [samples], with a real-time constraint $\tau$ [s] (i.e. its throughput must be $L/\tau$ [samples/s]).
The theoretical complexity of the algorithm is known, both in terms of arithmetic operations (additions, multiplications and comparisons) and memory accesses.
Is there any rule of thumb to get a (rough) estimate of the power consumption of this algorithm for typical hardware implementations (e.g FPGA, ASIC, General Purpose Processor, etc.)?