Please refer to the paper Splitting the Unit Delay - Tools for fractional delay filter design by Laakso, Valimaki et.al.
I am not able to visualize how the fractional delay is obtained by resampling the shifted version of the impulse response of the ideal filter as described in the following para.
When the desired delay D assumes an integer value, the impulse response Eq. 12 reduces to a single impulse at n = D, but for noninteger values of D the impulse response is an infinitely long, shifted and sampled version of the sinc function (Fig. 3). Unfortunately, the ideal impulse response is not only infinitely long but also noncausal, which makes it impossible to implement it in real-time applications.
Equation 12 gives an answer to the original problem, i.e., where the delayed signal value should be placed as it cannot be put "between the samples." In the ideal case, it is to be spread over all the discrete-time signal values, weighted by appropriate values of the sinc function.
Also, suppose the minimum unit delay supported by a system is D, can we derive fractional delays lesser than D with this technique or only greater than D? Does this in any way overcome system limitation w.r.t minimum tap delay resolution(splitting the unit delay as the name suggests)? Or is it only useful for implementing fractional or irrational rate conversions within bounds of the hardware?