Splitting the Unit Delay

Question

Please refer to the paper Splitting the Unit Delay - Tools for fractional delay filter design by Laakso, Valimaki et.al.

I am not able to visualize how the fractional delay is obtained by resampling the shifted version of the impulse response of the ideal filter as described in the following para.

When the desired delay D assumes an integer value, the impulse response Eq. 12 reduces to a single impulse at n = D, but for noninteger values of D the impulse response is an infinitely long, shifted and sampled version of the sinc function (Fig. 3). Unfortunately, the ideal impulse response is not only infinitely long but also noncausal, which makes it impossible to implement it in real-time applications.

Equation 12 gives an answer to the original problem, i.e., where the delayed signal value should be placed as it cannot be put "between the samples." In the ideal case, it is to be spread over all the discrete-time signal values, weighted by appropriate values of the sinc function.

Also, suppose the minimum unit delay supported by a system is D, can we derive fractional delays lesser than D with this technique or only greater than D? Does this in any way overcome system limitation w.r.t minimum tap delay resolution(splitting the unit delay as the name suggests)? Or is it only useful for implementing fractional or irrational rate conversions within bounds of the hardware?

Answer 1

For example a delay of 0.75 sampling periods would have an impulse response like this (red squares sampled from the blue delayed sinc):

Time (horizontal axis) unit is sampling periods. That kind of a filter is not causal as there are non-zero samples at negative times. None of the samples is zero, no matter how far left or right you go. That's what they meant by spreading all over.

About your second question, I have no access to the paper but I know that such all-pass fractional delay filters can be made arbitrarily good (approaching sinc), and the latency increases as you increase filter order. If you want very short latency, you then will also have a very low-order filter, which is of very poor quality as it is completely missing the left side of the sinc. It is a tradeoff between quality and latency, and you probably don't want to trade away all quality.

Answer 2

The ideal delay has a frequency response of: $$ H(e^{j\omega}) = e^{-j\omega D} $$ this has impulse response $$ h(n) = \mbox{sinc}(n - D) = \frac{\sin(\pi(n-D)}{\pi(n-D)}. $$ For $D$ an integer, this just becomes: $$ h(n) = \delta(n-D) $$ where $\delta$ is the Kronecker delta.

That means there is no resampling, so I am not sure where you get that from (it's not in your quoted text).

I am not quite sure what you are trying to achieve with your last paragraph. Can you please expand on it a bit? It sounds like you're wanting to make a non-causal system (one that overcomes a fundamental latency in your hardware system). But perhaps I am mistaken.

Answer 3

%ideal case

t=-8:0.1:8;

f=sinc(t);

n=0;

i=1:17

x(i)=f(1+(10*n));

n=n+1;

end

t2=-8:8;

plot (t,f);

hold on;

stem(t2,x);

%delay by 2.3

t=-8:0.1:8;

f=sinc(t);

n=1;

for i=-8:0.1:8

y(n)=sinc(i-2.3);

n=n+1;

end

n=0;

for i=1:17

z(i)=y(1+(10*n));

n=n+1;

end

t2=-8:8;

figure

plot(t,y);

hold on;

grid;

stem(t2,z);