In my implementation of minBLEP, overlapping minBLEPs result in a DC bias as the frequency increases. This is because each minBLEP correction (i.e. the minBLEP minus the aliased step) has a DC bias.
Here's a frequency sweep from 100Hz to 15kHz. The second signal shows the number of active BLEPs.
Interestingly, the minBLEP paper (http://www.cs.cmu.edu/~eli/papers/icmc01-hardsync.pdf) acts as if the DC woes are all solved by switching from integrating impulses to placing BLEPs. There's no mention of correcting DC when lots of BLEPs overlap.
Should I just add a DC-blocker at the end? Is that what is generally done?
Also, why is it important that the BLEPs are minimum phase? Using linear phase BLEPs would alleviate the DC bias, at the cost of delaying the oscillator output by half the length of the BLEP.