Lets say we want implement simply the mean with constant coefficients. So all b's are set to e.g. b=0.5. In this case I do not understand the delay line in the picture below.
I mean I understand it for von Neumann, Harvard architectures.., but how about if I just calculate everything on parallel FPGA? Shouldn't be possible to implement the whole structure without any delays? (..because it is all parallel and there is no feedback) or is it in practice just not possible?
(What I would understand is that there is maybe a delay at the end when the summation takes place)