I am trying to include the ability to have sub-clock delays on an FPGA system's data bus without the need of fractional delay filters. I am using a Xilinx V6 part, and could utilize its IODELAYE1 instance, but the max delay it can create is less than half a period, and the parts cannot be cascaded.

Is there theory for how to to do sub clock delays of data buses within a system?

  • $\begingroup$ What do you mean by "delay?" Are you wanting to add fractional-sample delay to a digitized signal that you're communicating over that bus? Or do you need some absolute time delay applied to the actual signalling that occurs on the bus lines? Those are two very different problems, and from glancing at Xilinx's documentation, I'm still not sure which the IODELAYE1 module is supposed to do. $\endgroup$ – Jason R Apr 16 '15 at 13:42
  • $\begingroup$ @JasonR I am sampling a signal, attenuating it, delaying it in a buffer, and outputting it out a DAC. The FPGA is running at 200MHz, so I have 5ns step delays. I am trying to find a way to delay a signal by .1ns (for instance), without resorting to fractional delay filters. $\endgroup$ – toozie21 Apr 16 '15 at 14:08
  • $\begingroup$ What is the purpose of inserting this delay? What is the expected result of the all process? $\endgroup$ – Moti Apr 17 '15 at 14:49
  • $\begingroup$ @Moti, I am attempting to add a delay-line into a signal path (think multipath). $\endgroup$ – toozie21 Apr 17 '15 at 18:46
  • $\begingroup$ Any delay will suffice? What is the limit of an external clock rate you may use with the FPGA? What resolution of a variable delay is desired? $\endgroup$ – Moti Apr 18 '15 at 17:24

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