I know that a general purpose microprocessor requires 18 operations to perform each butterfly of the FFT, but I do not understand how does using using a DSP or FFT chip improve FFT processing?
Any thoughts?
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My information may be a bit dated and the information may vary depending on the exact DSP chip you look at. The memory architecture on DSP chips often have multiple memories which can be accessed simultaneously. As an example look at the Harvard Memory Architecture. The instruction set on DSP chips is also highly specialized to make efficient use of this memory architecture. Often manufacturers provide library code for the FFT's because it would take a typical developer awhile to optimize the code by hand.
The memory on GPUs tends to be a hierarchy of caches, starting with a fast but small cache and then going to slower main memory.
DSP chip often have memory dedicated to storing the FFT twiddle factors i.e. the sin() and cos() factors. On GPUs these factors can be stored in the cache but it is usually not explicit and can not be guaranteed.
The output of the FFT is not usually in order i.e. the frequency bins do not appear as bin 1, bin 2, bin 3 .... Instead they come out in bit reversed order. DSP chips usually have an explicit bit reversed addressing mode, thus allowing efficient access to the FFT output. On GPUs this addressing mode is not used because it used so infrequently.
Hope that helps.
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$\begingroup$ "The output of the FFT is not usually in order i.e. the frequency bins do not appear as bin 1, bin 2, bin 3 .... Instead they come out in bit reversed order." BTW, that is not always the case. it depends on whether it's "Decimation-in-Time" or "Decimation-in-frequency" and there are variants of those. just as likely, it's the input to the FFT that must be in bit-reversed order and the output comes out in normal order. $\endgroup$ – robert bristow-johnson Dec 10 '14 at 20:31
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In addition to the memory differences that David pointed out, DSP chips have multiple multiply/accumulate (MAC) units. MAC is a very common signal processing operation that is the basis of filter and FFT/iFFT operations. Some DSP chips that I used in the past had six MAC units, which allowed them to speed up the FFT operations in two ways: they could do six MAC operations at once, and the MAC operation itself would take one clock cycle while on a general purpose microprocessor each MAC would take at least two clock cycles since it would be a multiply followed by an add.
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Further more, DSPs have dedicated hardware loop unit that frees the DSP from doing software loop.
Software loop: execute the loop content, increment the cycle variable, check condition, jump back if condition was met
Hardware loop: you tell the hardware how many times you want to execute a specific address range, and the hardware will take care of the rest.
There is no additional looping overhead.
David mentioned that there is a bit reverse addressing mode for reading the FFT results faster without addressing overhead in software, but there is also a modulo N addressing mode, that is capable of constructing circular buffers with no software boundary checking and rewinding.
