In my filter the fs=300MHz. and no. of coefficients is 31. I have following queries. (1) what will be the number of multiplications per second? (2) can multiplication be done in one clock cycle? (3) why normally multiplication per second is calculated and not addition/substraction per second in the filter implementation?
To answer your questions:
- The number of multiplies is the number of taps times the number of sample per second. Given a sampling rate of 300MHz and 31 taps, you will have to do 9300 million multiplies per second.
- As Paul R says, whether a multiply can be done in one cycle depends on the processor. Some can, some can't, and some appear to by having a long pipeline - once the pipeline fills, the result of one multiply comes out per cycle. You would have to find out what processor you are using to determine how many cycles it takes for each multiply. Also note, this varies also with the type of number you are working with. Integer multiplication is usually faster, but can cause you other difficulties (it is harder to do signal processing with integers.)
- As Paul R says, really only the multiplies are of interest since most processors have a combined multiply and add instruction. If you are working with a processor without that type of instruction, though, you will have to remember to count the adds when budgeting your clock cycles. Since there are as many adds as multiplies when doing an FIR, knowing how many multiplies there are also tells you the number of adds.
It really depends on what CPU you are using, but most modern CPUs (including DSPs) can do a fused multiply-add in one instruction, so you effectively get the addition for free. Operations such as an FIR filter typically require N multiplies and N adds, so this can be treated as N fused multiply-add instructions. If your CPU can issue one multiply-add per cycle then you would need N clock cycles per output point.