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I've been trying to get my head around digital plls from knowing nothing and seen that most examples only use the positive zero crossing, not the negative. I've tried to find the answer but the best i could find is a textbook that said "complications arise when using the negative zero crossing so this type of PLL isn't as common" without further explanation.

The only reason that i can think of is that it would require more processing, but surely this would be worthwhile as you would be able to achieve faster lock times?

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  • $\begingroup$ i don't think it would be much faster lock time with both positive and negative. essentially the PLL is functioning as a sorta primitive pitch detector, or inverse VCO function. because of what's unknown about the input waveform, in need not be 50% duty cycle with equal spacing between adjacent positive and negative crossings, you will not have a decent lock until you get two adjacent positive crossings or two adjacent negative crossings. $\endgroup$ – robert bristow-johnson Sep 7 '14 at 21:18
  • $\begingroup$ @robertbristow-johnson I dont know much about VCO's or pitch detectors so cant really comment on the first part. But my basic understanding is that at every zero crossing of the input signal and the generated signal the filter changes the phase\frequency of the generated signal, and if this is happening twice per cycle instead of once per cycle I see no reason why it shouldn't lock twice as fast. (like i said I'm quite new to PLL's so may be making some pretty ignorant conclusions) $\endgroup$ – Darren Lanigan Sep 7 '14 at 21:42
  • $\begingroup$ well, i dunno how to begin. you first need to understand the meaning of a VCO, or in the pure digital domain, an NCO. then the thing in a PLL that is essential to know about is the "phase discriminator". that's where some of this concern about zero crossings comes about. then, it might be useful to learn a little about what a servo-mechanism is (in control theory) and maybe what a "PID controller" is. these are the essential components of a PLL. $\endgroup$ – robert bristow-johnson Sep 8 '14 at 16:32
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Getting accurate lock when using both edges or zero-crossings requires that the duty cycles of both the PLL local oscillator and the reference signal match and/or be as stable as the frequency. If the duty cycles don't match when using both edges, then you would have to filter out some twice per cycle jitter which could well slow down lock speed.

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