A little background: I have an FPGA (running at 200MHz) that I am creating multipath events using buffers, all of that works. I take RF, mix down to IF, sample, make adjustments, out the DAC, and back up to RF. I use a windowed-sinc algorithm (like described here).
To do fractional delays, I compute the coefficients in a Java app and pass them to the FPGA. Each coefficient is a separate tap in the path on the FPGA, and then everything is summed up before outputting.
Like I mentioned, this all works, but I would like to make it work better. What I see is that for delays that work out to be closer to the middle of an FPGA clock "bin", I get the worst results. When the delay is closer to one of the edges of a bin I get better results.
As a test, I have 2462MHz for my RF, 2437MHz for my LO, and get an IF of 25MHz (just using pure tones out a signal generator). I have the tone going straight through on one tap, and I sum it with a fractional delay of itself. I looked at the output signal level on a spectrum analyzer for the first 15 completely out of phase points and plotted the results (in an ideal world they would cancel each other out). In this image the very first plot is actually where the second tap has a delay of 0 (completely in phase) to give a point of reference:
As you can see, the out of phase signals that fall near the beginning and end of a bin perform pretty well (and seem totally acceptable to me), the ones that fall near the center of a bin have the hardest time cancelling out. It might be acceptable (and as good as I can do), but I am curious if there is a way to perform better.
As an FYI, if I look at points within the first 2 periods of the RF signal (not just the 180 degree out of phase points) at 0.05ns increments, it looks very nice and smooth, the only thing that catches your eye is that there is a slight rise to the output, but that can be attributed to the fact that as I go along, I am getting closer to the center of a bin, and the results are getting worse.