This is problematic because I don't see any guarantees that a pair of those chips will provide you with same end-to-end latencies. You can probably cheat a bit if you clock both chips in the pair with the same clock, and provide the pair with a common synchronous reset signal.
Assuming the end-to-end latency is equal down to a single sample, you can leverage the fact that this chip family can take digital audio input and provide digital audio output. Thus you can sample the audio at a double data rate, and split it digitally between two chips using a bit of discrete logic or a small CPLD. The reverse of this process can be applied at the receiving end.
If you wish to align the signals at the receiving end in spite of no provisions for this by the chipset itself, you can be inserting synchronization marks (single-sample clicks) at the transmitting end. Those clicks are easy to detect on the receiving end, and can be "fixed" by interpolating over two adjacent samples. If the clicks are sent on a random schedule - say uniformly distributed between 0.5 and 2 seconds, they won't appreciably affect the signal. Any errors from the click removal will be spread-spectrum.