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Here is a radio chip for audio that sends at a CD-level data rate. Could you sample an analog signal (for instance from a guitar pick-up or microphone) in such a way that you could transmit using two radio chips (and receive using two radio chips), then recombine the signal on the receiver side into one that has double the data rate of the same basic circuit that uses only one transmitter chip (and one receiver)?

Also can this be done with an analog circuit rather than expensive A/D converters?

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  • $\begingroup$ Is the first part of the question about that specific chip or whether that's possible in general? $\endgroup$ – jan Jun 22 '14 at 23:29
  • $\begingroup$ If you're looking to do this with analogue hardware then electronics.stackexchange.com would probably be the best place to ask this question. $\endgroup$ – Paul R Jun 23 '14 at 7:03
  • $\begingroup$ data rate is the product of the sample rate and bit-depth. Which of these two parameters do you want to double? $\endgroup$ – pichenettes Jun 23 '14 at 7:56
  • $\begingroup$ Sorta sounds like you're heading towards a perfect reconstruction filter bank or some other filter bank (see this review article for a brief introduction: authors.library.caltech.edu/6798/1/VAIprocieee90.pdf), but this may be totally off from your intentions. $\endgroup$ – Batman Jun 23 '14 at 11:00
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This is problematic because I don't see any guarantees that a pair of those chips will provide you with same end-to-end latencies. You can probably cheat a bit if you clock both chips in the pair with the same clock, and provide the pair with a common synchronous reset signal.

Assuming the end-to-end latency is equal down to a single sample, you can leverage the fact that this chip family can take digital audio input and provide digital audio output. Thus you can sample the audio at a double data rate, and split it digitally between two chips using a bit of discrete logic or a small CPLD. The reverse of this process can be applied at the receiving end.

If you wish to align the signals at the receiving end in spite of no provisions for this by the chipset itself, you can be inserting synchronization marks (single-sample clicks) at the transmitting end. Those clicks are easy to detect on the receiving end, and can be "fixed" by interpolating over two adjacent samples. If the clicks are sent on a random schedule - say uniformly distributed between 0.5 and 2 seconds, they won't appreciably affect the signal. Any errors from the click removal will be spread-spectrum.

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