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I conducted a research on how to implement a QPSK demodulator. I found out the Quadrature QPSK demodulation technique which seems very straight forward. Here is what i understood from the explanation of the block diagram, and would like to confirm from this platform if my understanding is right. From the block diagram below, I am meant to do the following for a 2048 bits QPSK modulated signal:

  1. Split the incoming 2048 bits of QPSK modulated signal into the I and Q phase
  2. Multiply the 1024 bits in the I phase by the recovered carrier
  3. multiply the other 1024 bits in the Q phase by the 90 shifted recovered carrier

My question is what do I do to this sets of I and Q phase outputs in order to get my demodulated bits ?

Most explanations I have seen just says it passes through a decision maker, but none has gone the extra length to explain what really happens within the decision maker

QPSK DEMODULATOR

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  • $\begingroup$ You don't do any of the three items on your list when implementing a QPSK demodulator; you do what is shown on the block diagram and then use baseband matched filters/correlators followed by samplers and hard-limiters to convert the LPF output into data bits in the I and Q branches. This answer and the references cited therein have lots of information about matched filters/correlators especially in the baseband. $\endgroup$ – Dilip Sarwate Mar 23 '14 at 16:17
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Your block diagram is correct. However, it seems to me that your understanding of how to implement it is not. There are no 'bits' in the modulated signal! The input signal is a noisy analog bandpass signal, and the I and Q components are derived from this signal as shown in the block diagram: by demodulating and filtering the incoming signal. Then this (complex) signal is sampled at the symbol rate (you may need timing recovery to know when to sample) and fed to a slicer. The slicer decides which of the four possible symbols was (probably) transmitted in each symbol interval. After the detected symbols are known you simply decode each symbol according to the coding in the transmitter (each symbol carries two bits).

EDIT: I didn't mention matched filters even though they were emphasized in Dilip's comment. For an optimum receiver they are of course necessary, but given the level of the question it seems to me that the block diagram is OK, and that the idea is probably that it should be implemented as is. Even though it will result in a sub-optimum receiver it can perform well under mild channel conditions. The only real difference is the type of low-pass filter used (matched to the transmitted pulses or just eliminating out-of-band noise).

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  • $\begingroup$ The challenge is that I need an understanding of what goes on in the slicer (how the decision is made) because I am meant to write a code for this $\endgroup$ – Nazario_Jnr Mar 23 '14 at 18:43
  • $\begingroup$ The slicer just chooses the symbol of the original QPSK constellation that is closest to the received (noisy) symbol. So you basically have to compute distances in the complex plane. $\endgroup$ – Matt L. Mar 23 '14 at 18:48
  • $\begingroup$ Still a little too ambiguous. Can you break it down a little more $\endgroup$ – Nazario_Jnr Mar 23 '14 at 18:53
  • $\begingroup$ After sampling the I and Q components, you have a complex signal I+jQ, which is simply a complex number in each symbol interval. You compare this complex number to the original (complex) QPSK symbols used in the transmitter, and you choose as detected symbol the original symbol which is closest to the received symbol. $\endgroup$ – Matt L. Mar 23 '14 at 19:04
  • $\begingroup$ @MattL. For the diagram shown, the signals in the I and Q branches are sliced individually, not as complex signals, and the decision in each branch can be as simple as the demodulated data bit being 1 or 0 according as the signal is positive or negative (assuming that the LPF blocks any DC from getting through.) $\endgroup$ – Dilip Sarwate Mar 23 '14 at 21:10

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