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Some background: I am putting a sig-gen signal through an ADC, into an FPGA where I can modify it, out a DAC and up to a SpecAn. All that works fine.

I am experimenting with fractional delay filters, coefficients, and IF values (which are just my sine wave coming in for testing). I sample at 200MHz, and I have played with IFs of 25MHz, 50MHz, 66.667MHz and other in between. What I do on the FPGA is take the inputted signal, and sum it with a delayed copy of a signal (think multipath). The delay is being varied by using a fractional delay filter to create the copy (either 3 coefficients or 7 right now; all the below is for 7 coefficients).

My question is, what is the relationship between the number of coefficients I use, and the frequency of the IF? I think I am missing something fundamental (and probably easy), but I can't see what.

Here is a plot of the summations of the 25MHz signal with 7 coefficients on the fractional delay. The y-axis is the signal level (dBm) and the x-axis is the amount of delay. I stepped from 0 clock delay to 12 clocks (60ns) in 0.4 clock increments (2ns). You can see the in-phase additions at clocks delays 0 and 8, and the out of phase cancellations at 4 and 12 clock delays. 25MHz IF, 7 fractional delay coefficients

Next is the same sort of plot, but the IF is 66.667MHz and I go from 0 clock delays to 3 clocks delays (15ns) in 0.1 clock (0.5ns) increments. Here we should be in-phase at 0 and 3 clocks delays, and out of phase at 1.5. 66.667MHz IF, 7 fractional delay coefficients

What you can see in the second plot is that there seems to be a lag in the prediction. I actually have peaks just after where I would expect to see them (delays 0 and presumably 3), and my out-of-phase signal seems to appear after where I would expect it as well (1.5 clocks). There also appears to be more unevenness and the signal isn't as steady as the first plot (which was nearly as perfect and smooth as I could expect).

I understand that the faster IF is going to be harder to predict, but I feel like there is a relationship that I am missing between the IF, fractional delay coefficients, and maybe even sample rate.

Can anyone enlighten me?

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  • $\begingroup$ The 7-tap filter is probably attenuating and giving a non-flat delay above 50 MHz. By adding taps, you increase the useful bandwidth of the filter. Look at the gain and group delay of your filter vs input frequency to see this. $\endgroup$ – John Jan 10 '14 at 19:40
  • $\begingroup$ That is probably a good idea, but I am not sure that it will be that straightforward. Right now I am implementing the first equation from this paper: acoustics.hut.fi/~vpv/publications/icassp00-fd.pdf in Java and passing the tap values to the FPGA... $\endgroup$ – toozie21 Jan 13 '14 at 13:34

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