I'm working on improving the modem communication speed that can be achieved over a 10km cable. The current modem achieves a speed of 9600 bps via hardware (phase locked loop) and I'm looking for ways to at least double this, and do it all in firmware. Here are some specs for the project.
- Length: 10,000m
- Capacitance: 1.48μF (148pF/M)
- Resistance: 320 Ω (32 Ω/km)
- 10 Vpp (+10 V to -10 V) @ 250 mA
- Can be used for Amplitude and Frequency modulation
- Currently cannot perform phase modulation
Available bandwidth on cable
- 30 KHz to 100 KHz
- Attenuation: 100KHz signal results in a third of the amplitude of the 30KHz signal
Current method of modem communications (want to improve)
- A hardware implemented Phase Locked Loop (PLL)
- Achieves a speed of 9600 bps
The aim is to improve the 9600 bps speed and also to implement the modem in firmware. The firmware target is an ARM based 32-bit microcontroller - Infineon's XMC4500 with onboard ADC (firmware to be written in C). I have a working prototype, but the best I can achieve so far is 10,500 bps which is only a small improvement over the current system. The method used was to implement FSK demodulation using the Goertzel algorithm. I was detecting 4 frequencies in the range of 40KHz to 80Khz, which gives 2 bits per signalling period. On the microcontroller performance, I've found that 4 frequencies is the maximum number that can be attempted using the Goertzel method. Also the microcontroller ADC's practical maximum sampling rate is 700 KHz.
Does anyone have a suggestion how to achieve a decent speed improvement using frequency and/or amplitude modulation with such limitations as these? I'm new to DSP so I've likely missed some other better techniques that could be used.
Many thanks in advance.
PROGRESS UPDATE (10/10/2013)
Since posting this question and after some simulation and testing, the communications scheme has been changed to be asymmetrical since only the downlink side actually needed to be upgraded. The uplink speed remains as is - a PLL running at 9600 bps, but the downlink speed ends up being a faster ~64,000 bps, with the downlink demodulator hardware running on something equivalent to PC level.
This hardware upgrade enables the use of an FFT and an 8-bit symbol using 8 frequencies. The FFT parameters being used are a sample rate of 512,000 SPS and a number of bins of 64. The frequencies being detected are in the range of 32,000 Hz and upwards, with a spacing of 8,000 Hz. The ADC is 12-bit. I've also implemented Reed-Solomon forward error correction, which may be used to reduce error rates.