clock + phase recovery

Question

I am working on the implementation phase and time recovery algorithm and have doubts. Could you please explain to me some question?

1. PLL for time and phase recovery

I have found I can use PLL not only for a carrier phase correction but also for time. Is there difference in implementation?

Reference: Digital communications a discrete-time approach by Rice

2. what should be first: phase or time recovery?

Answer 1

I like the Rice's book as it gives enough details and explanations to be able to get to working implementation with a full understanding of what is actually happening. So the following is basically a citation from Rice.

1. What are the differences in PLL implementation?

A phase locked loop (PLL) in general has three basic components: a phase detector, a loop filter and a voltage controlled oscillator (VCO) arranged in a feedback system (see Appendix C in Rice's book). Digital PLL will have a somewhat similar structure. The goal of the PLL is to force the phase error to be zero.

Any PLL holds this basic structure. But for the tasks of synchronization (carrier and timing recovery) the particular implementation of PLL will depend on the algorithm you choose for a phase detector. Also it differs in where the feedback connection of the PLL goes.

2. What should be first: carrier or timing recovery?

In the section "10.1 Advanced Discreet-Time Architectures" Rice gives the review of different receiver architectures. For example, this is a "third generation discrete-time detector":

It shows the placement of PLLs for carrier recovery and symbol timing. Here you can see, that corrections from Symbol Timing PLL occur before the ones from Carrier Phase PLL. Note, that Rice also describes other architectures, which differ in where the feedback connections go.

Answer 2

A receiver needs to synchronize on those two timings in order to demodulate with best performance:

• Transmitter symbol rate
• Transmitter carrier

Synchronization state of the art way is to use a PLL. You need two loops processing at the same time. The same PLL architecture can be used for both synchronizations but instantiated separately. That is the case for the filtering part of the loop.

Except:

• Each loop has a different timing error detector: One detects symbol rate error and the other carrier phase error. Different algorithms for each.
• The feedback correction is applied in different areas in the chain: Symbol rate feedback is applied on a resampler, carrier error correction where the frequency translation is done.

Also important, a PLL is a fine synchronization. Which means that if you have a too large offset it won't be able to synchronize alone. A process ahead in the chain should perform the coarse synchronization.

Timing error detector for each loop should be smartly selected. As they can interfere between themselves. For example Gardner when applicable is able to estimate the symbol rate timing error with a carrier phase offset inside.