Timeline for ADC Aliasing in RFSoC
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 21 at 14:43 | comment | added | MIchaelNilan | @YairM Thank you for the info will check surely | |
| Oct 18 at 6:00 | comment | added | Yair M | The RFSoC implements various digital LPFs which may be cascaded. This is configurable. If I remember correctly, details appear in PG269. The filter taps appear there too, and you can plot the frequency response in MATLAB | |
| Oct 17 at 17:27 | vote | accept | MIchaelNilan | ||
| Oct 17 at 10:34 | comment | added | MIchaelNilan | I am using the available ADC/DACs in the ZCU1275 RFSoC | |
| Oct 17 at 6:03 | comment | added | Yair M | What digital LPF are you using for decimation? | |
| Oct 16 at 22:51 | answer | added | Dan Boschen | timeline score: 0 | |
| Oct 16 at 21:28 | history | asked | MIchaelNilan | CC BY-SA 4.0 |