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robert bristow-johnson
robert bristow-johnson
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As far as I know now, most ADC and DAC chips communicate to their CPU or DSP chip over a serial protocol with 3 wires (word/frame clock, bit clock, data) and the data is represented as a twos-complement integer. But you should consult the spec sheet of the ADC/DAC chip and get all of the particulars. Representations such as Q6.10 or such really are in the mind of the programmer. The fixed-point twos-complement bits are exactly the same whether you consider it Q1.15 or Q2.14 or Q6.10 . That scaling factor is up to the programmer.

Now the Q scaling of the coefficients, that's a little different. That gets defined by the way you extract the 16-resultbit result out of the 32-bit words that result when you multiply two 16-bit numbers together. You really do have to consider that in advance.

If you're doing an IIR, numerical issues can get a little funky and you do need to worry about them. Maybe this answer will give you some insight in how to think about doing fixed-point IIR.

As far as I know now, most ADC and DAC chips communicate to their CPU or DSP chip over a serial protocol with 3 wires (word/frame clock, bit clock, data) and the data is represented as a twos-complement integer. But you should consult the spec sheet of the ADC/DAC chip and get all of the particulars. Representations such as Q6.10 or such really are in the mind of the programmer. The fixed-point twos-complement bits are exactly the same whether you consider it Q1.15 or Q2.14 or Q6.10 . That scaling factor is up to the programmer.

Now the Q scaling of the coefficients, that's a little different. That gets defined by the way you extract the 16-result out of the 32-bit words that result when you multiply two 16-bit numbers together. You really do have to consider that in advance.

If you're doing an IIR, numerical issues can get a little funky and you do need to worry about them. Maybe this answer will give you some insight in how to think about doing fixed-point IIR.

As far as I know now, most ADC and DAC chips communicate to their CPU or DSP chip over a serial protocol with 3 wires (word/frame clock, bit clock, data) and the data is represented as a twos-complement integer. But you should consult the spec sheet of the ADC/DAC chip and get all of the particulars. Representations such as Q6.10 or such really are in the mind of the programmer. The fixed-point twos-complement bits are exactly the same whether you consider it Q1.15 or Q2.14 or Q6.10 . That scaling factor is up to the programmer.

Now the Q scaling of the coefficients, that's a little different. That gets defined by the way you extract the 16-bit result out of the 32-bit words that result when you multiply two 16-bit numbers together. You really do have to consider that in advance.

If you're doing an IIR, numerical issues can get a little funky and you do need to worry about them. Maybe this answer will give you some insight in how to think about doing fixed-point IIR.

Source Link
robert bristow-johnson
robert bristow-johnson
  • 21.4k
  • 4
  • 39
  • 78

As far as I know now, most ADC and DAC chips communicate to their CPU or DSP chip over a serial protocol with 3 wires (word/frame clock, bit clock, data) and the data is represented as a twos-complement integer. But you should consult the spec sheet of the ADC/DAC chip and get all of the particulars. Representations such as Q6.10 or such really are in the mind of the programmer. The fixed-point twos-complement bits are exactly the same whether you consider it Q1.15 or Q2.14 or Q6.10 . That scaling factor is up to the programmer.

Now the Q scaling of the coefficients, that's a little different. That gets defined by the way you extract the 16-result out of the 32-bit words that result when you multiply two 16-bit numbers together. You really do have to consider that in advance.

If you're doing an IIR, numerical issues can get a little funky and you do need to worry about them. Maybe this answer will give you some insight in how to think about doing fixed-point IIR.