FPGA is only user to verify the initial RTL which is specifically written to do each of the task listed below. Once the verification is done there is a tape out and everything is implemented in hardware accelerators as below. FPGA is wasteful of area and too power hungry which cannot be afforded in modem (low power device)

The LTE channel estimation is done as follows:

• The FFT of the incoming samples at receiver is taken post cyclic prefix removal. This is done in an FFT kernel in Hardware (specifically written RTL, not in FPGA)

• Then this result is fed to a memory where all the subcarriers are stored for this particular symbol (other symbols are stored in this memory as well).

• Then firstly all positions at which CRS (Cell Reference Symbol) is available are extracted for the symbol, the channel is estimated (MMSE or others) at the subcarriers corresponding to the CRS. This is done in a hardware accelerator. See figure below

• Then there is an interpolation done in between the CRS subcarriers to find the the channel estimate at non CRS subcarriers (wiener filters), this is called interpolation in frequency. This is also done in Hardware accelerators (i.e. RTL is written specifically for this)
• Now, CRS (per antenna port) is only transmitted in 2 symbols in a slot(for most of the transmission modes). It is transmitted in the first and $5^{th}$ symbol of a slot for normal CP. All the symbols for a full subframe are buffered and frequency interpolation is done at all symbols in which CRS is transmitted as explained above (see figure below)

• Then there is an interpolation done in time to get channel estimates for all symbols in between the symbols containing CRS, to get a channel estimate for all the subcarriers in the entire frequency grid. This is also done in the Hardware accelerators
• The CRS references positions are at every 6th subcarrier in frequency (linked to the coherence bandwidth) and similarly in time linked to coherence time

Once the there are channel estimates available for all subcarriers of 1 full subframe. It is sent for equalization/demodulation (this is also done in Hardware accelerators)

The reason for using Hardware accelerators over doing in Firmware speed. The reason for doing in accelerators over FPGA is area and power. accelerators have a smaller footprint and more power efficient

To the first question, by itself there is no limitation that an LTE channel can have for the phase shift. But there are limitations as to what can be estimated unambiguously by the receiver. Consider this situation: The maximum frequency offset that an LTE system can estimate is +/-7.5KHz (because subcarrier spacing is 15 Khz) anything above this frequency offset will wrap around to within the above specified range. Now since frequency offset shows up as phase in the signal multiplied with channel estimate the ambiguity will remain in unwrapped phase.

As to how then we measure frequency offsets more than +/-7.5Khz, that's another story :)

FPGA is only user to verify the initial RTL which is specifically written to do each of the task listed below. Once the verification is done there is a tape out and everything is implemented in hardware accelerators as below. FPGA is wasteful of area and too power hungry which cannot be afforded in modem (low power device)

The LTE channel estimation is done as follows:

• The FFT of the incoming samples at receiver is taken post cyclic prefix removal. This is done in an FFT kernel in Hardware (specifically written RTL, not in FPGA)

• Then this result is fed to a memory where all the subcarriers are stored for this particular symbol (other symbols are stored in this memory as well).

• Then firstly all positions at which CRS (Cell Reference Symbol) is available are extracted for the symbol, the channel is estimated (MMSE or others) at the subcarriers corresponding to the CRS. This is done in a hardware accelerator. See figure below

• Then there is an interpolation done in between the CRS subcarriers to find the the channel estimate at non CRS subcarriers (wiener filters), this is called interpolation in frequency. This is also done in Hardware accelerators (i.e. RTL is written specifically for this)
• Now, CRS (per antenna port) is only transmitted in 2 symbols in a slot(for most of the transmission modes). It is transmitted in the first and $5^{th}$ symbol of a slot for normal CP. All the symbols for a full subframe are buffered and frequency interpolation is done at all symbols in which CRS is transmitted as explained above (see figure below)

• Then there is an interpolation done in time to get channel estimates for all symbols in between the symbols containing CRS, to get a channel estimate for all the subcarriers in the entire time frequency grid. This is also done in the Hardware accelerators
• The CRS references positions are at every 6th subcarrier in frequency (linked to the coherence bandwidth) and similarly in time linked to coherence time

Once there are channel estimates available for all subcarriers of 1 full subframe. It is sent for equalization/demodulation (this is also done in Hardware accelerators)

The reason for using Hardware accelerators over doing in Firmware is speed. The reason for doing in accelerators over FPGA is area and power. accelerators have a smaller footprint and more power efficient

To the first question, by itself there is no limitation that an LTE channel can have for the phase shift. But there are limitations as to what can be estimated unambiguously by the receiver. Consider this situation: The maximum frequency offset that an LTE system can estimate is +/-7.5KHz (because subcarrier spacing is 15 Khz) anything above this frequency offset will wrap around to within the above specified range. Now since frequency offset shows up as phase in the signal multiplied with channel estimate the ambiguity will remain in unwrapped phase.

As to how then we measure frequency offsets more than +/-7.5Khz, that's another story :)