Timeline for Precompute parts of an FFT on streamed data inputs
Current License: CC BY-SA 4.0
30 events
| when toggle format | what | by | license | comment | |
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| Aug 25, 2020 at 15:29 | answer | added | Knut Inge | timeline score: 0 | |
| Aug 25, 2020 at 4:39 | answer | added | Bob | timeline score: 1 | |
| Aug 25, 2020 at 4:02 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
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| Jul 6, 2018 at 19:41 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Jun 6, 2018 at 17:36 | answer | added | hotpaw2 | timeline score: 1 | |
| Jun 6, 2018 at 14:44 | history | edited | Claudio Brasser | CC BY-SA 4.0 |
clarifications
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| Jun 6, 2018 at 14:43 | comment | added | Olli Niemitalo | @A_A sometimes I don't dare to link to a pdf with an unknown copyright status | |
| Jun 6, 2018 at 14:32 | comment | added | Claudio Brasser | @MarcusMüller Ah I get your point now. It's actually part of the project to code the FFTs by myself, it's not supposed to be competitive in terms of running time with highly optimized libraries. I was just curious if there is a way to achieve the above mentioned | |
| Jun 6, 2018 at 14:30 | comment | added | Marcus Müller | I ask for two reasons: 1. answers will be fundamentally different, because in digital logic, calculations are / can be fundamentally parallel. 2. Software runs on CPUs. Your software probably runs on a modern, large CPU. Modern CPUs have wide memory interfaces and large caches. It makes no latency difference to write 256 words or one word, so I'm not even sure you'd potentially be able at all to optimize things much if you're working on a modern CPU :) | |
| Jun 6, 2018 at 14:20 | history | edited | Claudio Brasser | CC BY-SA 4.0 |
DSP not DST, silly tipo
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| Jun 6, 2018 at 14:18 | comment | added | A_A | Please link papers :) (@OlliNiemitalo) | |
| Jun 6, 2018 at 14:13 | comment | added | user28715 | DST=“day light savings time”? Probably not. So could you define less used acronyms, please | |
| Jun 6, 2018 at 14:12 | comment | added | Marcus Müller | @ClaudioBrasser well, the cases in which you'd normally implement an FFT yourself rather than just using an existing library are typically not software, but you doing the calculation on an FPGA or in a especially designed ASIC in a place where due to some external constraint you can't use a ready-made FFT block. Hence, digital logic (as in: actually wired multipliers, adders, …). | |
| Jun 6, 2018 at 14:07 | comment | added | Claudio Brasser | @OlliNiemitalo Thank you, I'll take a look at it! | |
| Jun 6, 2018 at 14:07 | comment | added | Claudio Brasser | @MarcusMüller I'm sorry I don't quite understand what you mean by 'digital logic'? My implementations are all software based if that's your question? | |
| Jun 6, 2018 at 14:02 | comment | added | Olli Niemitalo | Gardner's 1995 paper "Efficient convolution without input-output delay" has something on combining smaller FFT results to get a bigger one. But I don't know if it is efficient if you don't need the smaller ones. | |
| Jun 6, 2018 at 14:02 | comment | added | Marcus Müller | I take this is digital logic, not software, right? | |
| Jun 6, 2018 at 14:01 | history | edited | Marcus Müller | CC BY-SA 4.0 |
added 9 characters in body
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| Jun 6, 2018 at 13:55 | review | First posts | |||
| Jun 6, 2018 at 14:26 | |||||
| Jun 6, 2018 at 13:54 | history | asked | Claudio Brasser | CC BY-SA 4.0 |