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I have a counter in my embedded system with f = 64 Mhz.

let's say its read value is $cnt_i$ where $i$ is the index of the time I sampled it. $$\Delta = cnt_{i+1} -cnt_i$$

let's say I take $\Delta^{'} = \Delta/64 = \Delta >>6$ where $>>$ is shift right operator.

I understand that the value of the actual counter now is equivalent to 1 Mhz but How can I show that.

$\Delta^{'} = \Delta/64 $ $[\Delta^{'}]_{sec} = \frac{\Delta}{64Mhz}*\frac{1}{64}$

but it is exactly the opposite, what do I miss?

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The last equation you have doesn't really make any sense. The relationship is straightforward: if you have a counter incrementing at 64 MHz and divide it by a factor of 64, then the result will be a counter that increments at 1 MHz. For every 64 ticks of the original counter, the divided one increments by one. –  Jason R Feb 18 '13 at 14:22
    
@JasonR I understand it but how you show it mathematically ? –  0x90 Feb 22 '13 at 21:52

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In order to show that a counter is running at a specific frequency, you need to take two readings spaced at some known time period apart and then calculate how many ticks would occur in one second. Say that you take two measurements from a monotonically-increasing counter at times $t_1$ and $t_2$. Their difference is:

$$ \Delta C = C_{t_2} - C_{t_1} $$

You can calculate the frequency of the counter from the difference as follows:

$$ f = \frac{\text{number of ticks}}{\text{time period}} = \frac{\Delta C}{\Delta t} = \frac{C_{t_2} - C_{t_1}}{t_2 - t_1} $$

In your example, if you divide both counter values $C_{t_1}$ and $C_{t_2}$ by a factor of 64 (for instance, by right-shifting by 6 bits), then the above equation becomes:

$$ f = \frac{1}{64}\frac{C_{t_2} - C_{t_1}}{t_2 - t_1} $$

Therefore, the action of dividing the counter's output value by 64 has the likewise action of dividing its output frequency by the same factor.

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